(dbSetEEQByLoc "SRAM32x256_1rw" "WEB" '(
		( ("m" "M3" 251745 36455))
		( ("m" "M2" 251745 36455))
		( ("m" "M1" 251745 36455))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "OEB" '(
		( ("m" "M3" 204585 0))
		( ("m" "M2" 204585 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[9]" '(
		( ("m" "M3" 179575 0))
		( ("m" "M2" 179575 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[8]" '(
		( ("m" "M3" 179100 0))
		( ("m" "M2" 179100 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[7]" '(
		( ("m" "M3" 194245 0))
		( ("m" "M2" 194245 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[6]" '(
		( ("m" "M3" 193710 0))
		( ("m" "M2" 193710 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[5]" '(
		( ("m" "M3" 193375 0))
		( ("m" "M2" 193375 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[4]" '(
		( ("m" "M3" 192950 0))
		( ("m" "M2" 192950 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[3]" '(
		( ("m" "M3" 208375 0))
		( ("m" "M2" 208375 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[31]" '(
		( ("m" "M3" 109770 0))
		( ("m" "M2" 109770 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[30]" '(
		( ("m" "M3" 109230 0))
		( ("m" "M2" 109230 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[2]" '(
		( ("m" "M3" 208055 0))
		( ("m" "M2" 208055 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[29]" '(
		( ("m" "M3" 108895 0))
		( ("m" "M2" 108895 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[28]" '(
		( ("m" "M3" 108470 0))
		( ("m" "M2" 108470 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[27]" '(
		( ("m" "M3" 123895 0))
		( ("m" "M2" 123895 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[26]" '(
		( ("m" "M3" 123575 0))
		( ("m" "M2" 123575 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[25]" '(
		( ("m" "M3" 123255 0))
		( ("m" "M2" 123255 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[24]" '(
		( ("m" "M3" 122780 0))
		( ("m" "M2" 122780 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[23]" '(
		( ("m" "M3" 137930 0))
		( ("m" "M2" 137930 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[22]" '(
		( ("m" "M3" 137390 0))
		( ("m" "M2" 137390 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[21]" '(
		( ("m" "M3" 137055 0))
		( ("m" "M2" 137055 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[20]" '(
		( ("m" "M3" 136630 0))
		( ("m" "M2" 136630 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[1]" '(
		( ("m" "M3" 207735 0))
		( ("m" "M2" 207735 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[19]" '(
		( ("m" "M3" 152055 0))
		( ("m" "M2" 152055 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[18]" '(
		( ("m" "M3" 151735 0))
		( ("m" "M2" 151735 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[17]" '(
		( ("m" "M3" 151415 0))
		( ("m" "M2" 151415 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[16]" '(
		( ("m" "M3" 150940 0))
		( ("m" "M2" 150940 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[15]" '(
		( ("m" "M3" 166090 0))
		( ("m" "M2" 166090 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[14]" '(
		( ("m" "M3" 165550 0))
		( ("m" "M2" 165550 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[13]" '(
		( ("m" "M3" 165215 0))
		( ("m" "M2" 165215 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[12]" '(
		( ("m" "M3" 164790 0))
		( ("m" "M2" 164790 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[11]" '(
		( ("m" "M3" 180215 0))
		( ("m" "M2" 180215 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[10]" '(
		( ("m" "M3" 179895 0))
		( ("m" "M2" 179895 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "O[0]" '(
		( ("m" "M3" 207260 0))
		( ("m" "M2" 207260 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[9]" '(
		( ("m" "M3" 174545 0))
		( ("m" "M2" 174545 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[8]" '(
		( ("m" "M3" 174865 0))
		( ("m" "M2" 174865 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[7]" '(
		( ("m" "M3" 187695 0))
		( ("m" "M2" 187695 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[6]" '(
		( ("m" "M3" 188305 0))
		( ("m" "M2" 188305 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[5]" '(
		( ("m" "M3" 188625 0))
		( ("m" "M2" 188625 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[4]" '(
		( ("m" "M3" 188945 0))
		( ("m" "M2" 188945 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[3]" '(
		( ("m" "M3" 201775 0))
		( ("m" "M2" 201775 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[31]" '(
		( ("m" "M3" 103215 0))
		( ("m" "M2" 103215 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[30]" '(
		( ("m" "M3" 103825 0))
		( ("m" "M2" 103825 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[2]" '(
		( ("m" "M3" 202385 0))
		( ("m" "M2" 202385 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[29]" '(
		( ("m" "M3" 104145 0))
		( ("m" "M2" 104145 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[28]" '(
		( ("m" "M3" 104465 0))
		( ("m" "M2" 104465 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[27]" '(
		( ("m" "M3" 117295 0))
		( ("m" "M2" 117295 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[26]" '(
		( ("m" "M3" 117905 0))
		( ("m" "M2" 117905 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[25]" '(
		( ("m" "M3" 118225 0))
		( ("m" "M2" 118225 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[24]" '(
		( ("m" "M3" 118545 0))
		( ("m" "M2" 118545 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[23]" '(
		( ("m" "M3" 131375 0))
		( ("m" "M2" 131375 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[22]" '(
		( ("m" "M3" 131985 0))
		( ("m" "M2" 131985 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[21]" '(
		( ("m" "M3" 132305 0))
		( ("m" "M2" 132305 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[20]" '(
		( ("m" "M3" 132630 0))
		( ("m" "M2" 132630 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[1]" '(
		( ("m" "M3" 202705 0))
		( ("m" "M2" 202705 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[19]" '(
		( ("m" "M3" 145455 0))
		( ("m" "M2" 145455 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[18]" '(
		( ("m" "M3" 146065 0))
		( ("m" "M2" 146065 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[17]" '(
		( ("m" "M3" 146385 0))
		( ("m" "M2" 146385 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[16]" '(
		( ("m" "M3" 146705 0))
		( ("m" "M2" 146705 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[15]" '(
		( ("m" "M3" 159535 0))
		( ("m" "M2" 159535 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[14]" '(
		( ("m" "M3" 160145 0))
		( ("m" "M2" 160145 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[13]" '(
		( ("m" "M3" 160465 0))
		( ("m" "M2" 160465 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[12]" '(
		( ("m" "M3" 160785 0))
		( ("m" "M2" 160785 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[11]" '(
		( ("m" "M3" 173615 0))
		( ("m" "M2" 173615 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[10]" '(
		( ("m" "M3" 174225 0))
		( ("m" "M2" 174225 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "I[0]" '(
		( ("m" "M3" 203025 0))
		( ("m" "M2" 203025 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "CSB" '(
		( ("m" "M3" 212230 0))
		( ("m" "M2" 212230 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "CE" '(
		( ("m" "M3" 214830 0))
		( ("m" "M2" 214830 0))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[7]" '(
		( ("m" "M3" 251745 319865))
		( ("m" "M2" 251745 319865))
		( ("m" "M1" 251745 319865))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[6]" '(
		( ("m" "M3" 251745 320575))
		( ("m" "M2" 251745 320575))
		( ("m" "M1" 251745 320575))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[5]" '(
		( ("m" "M3" 251745 325615))
		( ("m" "M2" 251745 325615))
		( ("m" "M1" 251745 325615))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[4]" '(
		( ("m" "M3" 251745 326325))
		( ("m" "M2" 251745 326325))
		( ("m" "M1" 251745 326325))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[3]" '(
		( ("m" "M3" 251745 331390))
		( ("m" "M2" 251745 331390))
		( ("m" "M1" 251745 331390))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[2]" '(
		( ("m" "M3" 251745 332100))
		( ("m" "M2" 251745 332100))
		( ("m" "M1" 251745 332100))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[1]" '(
		( ("m" "M3" 251745 337160))
		( ("m" "M2" 251745 337160))
		( ("m" "M1" 251745 337160))
		))
(dbSetEEQByLoc "SRAM32x256_1rw" "A[0]" '(
		( ("m" "M3" 251745 337875))
		( ("m" "M2" 251745 337875))
		( ("m" "M1" 251745 337875))
		))
